Design Verification Engineer
发布时间:2022-9-22 14:14
发布者:KT咨询
NO.400-【猎头职位:西安需要多位 Design Verification Engineer】联系人:Sophie-Song,邮箱:hr@kthr.com,微信也可查询职位了!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加,欢迎大家关注! 岗位职责: 1、Participate ASIC digital verification for various IP/SoC projects; 2、Create verification plans and execution; 3、Develop virtual prototype modeling for algorithm logic; 4、Develop DV architecture and verification environment; 5、Verification execution and sign-off. 岗位要求: 1、Excellent team working style; 2、Solid IP/SoC verification background; 3、Experience with IP/SoC sign-off; 4、Master with 2+ years working experiences on ASIC digital verification; 5、Production experiences on verification strategies and vPlan extraction and execution; 6、Familiar with SystemVerilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage; 7、CXL / DSP experience is an advantage; 8、Direct test at SoC level is a must, low level driver awareness is an advantage; 9、Project experiences on ARM buses, such as AXI/AMBA/APB is an advantage; 10、Familiar with verification tools; 11、Familiar with Linux, csh/Python or any script languages; 12、Good English skills (read and write); Additionally: 13、Having crypto(e.g. ECC, AES, RSA, SM2/3/4, TRNG…) knowledge is a plus; 14、Typical serial bus experiences, e.g. I2C, I3C, SMBus protocol knowledge is a plus. 福利:五险一金 补充医疗保险 员工旅游 绩效奖金 年终奖金 弹性工作 |
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