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STM32WLE5CC原理图

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发表于 2021-11-1 11:29:29 | 显示全部楼层 |阅读模式
关键词: STM32WLE5CC
电路原理图

所有功能
  • Radio
    • Frequency range: 150 MHz to 960 MHz
    • Modulation: LoRa®, (G)FSK, (G)MSK and BPSK
    • RX sensitivity: –123 dBm for 2-FSK(at 1.2 Kbit/s), –148 dBm for LoRa® (at 10.4 kHz, spreading factor 12)
    • Transmitter high output power, programmable up to +22 dBm
    • Transmitter low output power, programmable up to +15 dBm
    • Compliant with the following radio frequency regulations: ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 and the Japanese ARIB STD-T30, T-67, T-108
    • Compatible with standardized or proprietary protocols such as LoRaWAN®, Sigfox™, W-MBus and more (fully open wireless system-on-chip)
  • Ultra-low-power platform
    • 1.8 V to 3.6 V power supply
    • –40 °C to +105 °C temperature range
    • Shutdown mode: 31 nA (VDD = 3 V)
    • Standby (+ RTC) mode:360 nA (VDD = 3 V)
    • Stop2 (+ RTC) mode: 1.07 μA (VDD = 3 V)
    • Active-mode MCU: < 72 μA/MHz (CoreMark®)
    • Active-mode RX: 4.82 mA
    • Active-mode TX: 15 mA at 10 dBm and 87 mA at 20 dBm (LoRa® 125 kHz)
  • 内核
    • 32-bit Arm® Cortex®-M4 CPU
      • Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions
      • 1.25 DMIPS/MHz (Dhrystone 2.1)

  • Security and identification
    • Hardware encryption AES 256-bit
    • True random number generator (RNG)
    • Sector protection against read/write operations (PCROP, RDP, WRP)
    • CRC calculation unit
    • Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard)
    • 96-bit unique die identifier
    • Hardware public key accelerator (PKA)
  • Supply and reset management
    • High-efficiency embedded SMPS step-down converter
    • SMPS to LDO smart switch
    • Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds
    • Ultra-low-power POR/PDR
    • Programmable voltage detector (PVD)
    • VBAT mode with RTC and 20x32-byte backup registers
  • clock sources
    • 32 MHz crystal oscillator
    • TCXO support: programmable supply voltage
    • 32 kHz oscillator for RTC with calibration
    • High-speed internal 16 MHz factory trimmed RC (± 1 %)
    • Internal low-power 32 kHz RC
    • Internal multi-speed low-power 100 kHz to 48 MHz RC
    • PLL for CPU, ADC and audio clocks
  • Memories
    • Up to 256-Kbyte Flash memory
    • Up to 64-Kbyte RAM
    • 20x32-bit backup register
    • Bootloader supporting USART and SPI inteRFaces
    • OTA (over-the-air) firmware update capable
    • Sector protection against read/write operations


  • Rich analog peripherals (down to 1.62 V)
    • 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V
    • 12-bit DAC, low-power sample-and-hold
    • 2x ultra-low-power comparators
  • System peripherals
    • Semaphores for processor firmware process synchronization
  • Controllers
    • 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers
    • 2x USART (ISO 7816, IrDA, SPI)
    • 1x LPUART (low-power)
    • 2x SPI 16 Mbit/s (1 over 2 supporting I2S)
    • 3x I2C (SMBus/PMBus™)
    • 2x 16-bit 1-channel timer
    • 1x 16-bit 4-channel timer (supporting motor control)
    • 1x 32-bit 4-channel timer
    • 3x 16-bit ultra-low-power timer
    • 1x RTC with 32-bit sub-second wakeup counter
    • 1x independent SysTick
    • 1x independent watchdog
    • 1x window watchdog
  • Up to 43 I/Os, most 5 V-tolerant
  • Development support
    • Serial-wire debug (SWD), JTAG for the application processor
  • All packages ECOPACK2 compliant


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