(Sr.)Design Verification Engineer

发布时间：2021-5-21 16:15 发布者：KT咨询

NO.579-【猎头职位：上海、南京需要多位 (Sr.)Design Verification Engineer】联系人：Edward-Duan,邮箱：hr@kthr.com，微信也可查询职位了！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

岗位职责：

1、Develop verification collateral suitable for a variety of design implementations ranging from FPGAs to SOCs;

2、Drive DV tasks such as test planning and execution, coverage for digital and mixed-signal blocks;

3、Construct and execute test plans and perform coverage analysis;

4、Work closely and collaboratively with RTL and analog designers;

5、Work with US DV team to maintain and contribute to DV methodology and best practices.

岗位要求：

1、BS or greater in a relevant discipline such as Computer Science, Electrical Engineering, or Computer Engineering with at least 3 years of relevant work experience;

2、Logic simulation skills including testbench design, stimulus generation, coverage closure, equivalence-checking and debug;

3、Proficiency in UVM/VMM/eRM and a hardware description language such as SystemVerilog;

4、Strong software skills (C, C++, Python) to develop and support infrastructure and flows;

5、Experience with formal verification a plus;

6、Experience with mixed-signal simulation and/or modeling a plus;

7、Basic knowledge of Deep Neural Networks and Artificial Intelligence a plus;

8、English Fluency: High.

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(Sr.)Design Verification Engineer

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