关于ARM CORTEX-A8 S5PV210使用的内存相关配置参考

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S5PV210有两个独立的DRAM控制器，分别是DMC0和DMC1，其中，DMC0最大支持512MByte，DMC1最大支持1GByte，而 DMC0和DMC1又同时支持两个片选CS0和CS1。S5PV210的内存模块相比2440和6410来讲要更加复杂一些，要想正确的配置 S5PV210的内存，应该仔细阅读芯片手册相关部分，在配置参数时也应该适当的阅读下内存芯片的手册。

在技术手册里，S5PV210给出了以下几个解决方案：

关于地址映射方面：S5PV210的DMC跟6410和2440的DMC有个重要区别，S5PV210可以控制内存地址映射，DMC0的地址空间为 0x2000,0000~0x3fff,ffff，DMC1的地址空间为0x4000,0000~0x7fff,ffff，DMC可以通过配置寄存器来使 内存芯片映射到其内存段内的适当位置。这个配置在MEMCONFIG寄存器中。

如果设置chip_base为0x20：

(1)我们挂载的内存为128M，那么这个chip_mask应该设置为0xF8

(2)我们挂载256M内存时，chip_mask应该设置为0xF0

(3)我们挂载512M时，chip_mask应该设置为0xE0

(4)我们挂载1GB内存时，chip_mask就应该设置为0xC0。

以DMC0为例，当DMC0接收到来自AXI的0x2000,0000~0x3fff,ffff内的地址时，会作如下处理：

(1)将AXI地址的高8位与chip_mask相与得到结果，记为X。

(2)将X分别与MEMCONFIG0和MEMCONFIG1的chip_base相比较，如果相等，则打开相应的片选。

假如挂载的内存为128M，且CS0和CS1上分别挂了一片，那么128M=128*1024*1024=0x8000000，则128M内存的偏 移范围应该是0x0000,0000~0x07ff,ffff，高位剩余5位，那么，我们把MEMCONFIG0的chip_base设置为 0x20，chip_mask设置为0xF8，为了保持内存连续，则需要将MEMCONFIG1的chip_base设置为0x28，chip_mask 设置为0xF8，当AXI发来的地址为0x23xx,xxxx时，0x23&0xF8得到0x20，所以，会打开片选CS0，当AXI发来的地址 为0x28xx,xxxx时，0x28&0xF8得到0x28，所以，会打开片选CS1，依此类推。

特别的，当载在的内存芯片为8bank（8bank内存芯片一般为14/15行地址，10列地址，即容量一般为512M或者1G）时，由于CS1为 bank2引脚，为了保持CS0时钟处于片选状态，对于512M内存来讲需要将chip_mask设置为0xE0，这是因为 512M=512*1024*1024=0x2000,0000，也就是说，512M内存的偏移应该为0x0000,0000~0x1fff,ffff， 所以高位剩余3位，即0xE0，当然了，如果内存为1G=1024*1024*1024=0x4000,0000，即偏移为 0x0000,0000~0x3fff,ffff，高位剩余2为，故设置chip_mask为0xC0。这样，就会计算偏移这两个值了。

另外在附上s5pv210（飞凌ok210开发板）的内存初始化顺序，芯片手册上给出了常用内存类型的初始化序列，一般如果使用DDR2的内存的话，可以按照如下顺序进行初始化：

Initialization sequence for DDR2 memory type:

1.To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.

2.Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc  bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to 1 to turn on the PHY DLL.

3.DQS Cleaning:Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value  according to clock frequency and memory tAC parameters.

4. Set the PhyControl0.ctrl_start bit-field to 1.  

5. Set the ConControl. At this moment, an auto refresh counter should be off.

6. Set the MemControl. At this moment, all power down modes should be off.

7. Set the MemConfig0  register. If there are two external memo ry chips, set the MemConfig1 register.

8. Set the PrechConfig  and PwrdnConfig registers.

9. Set the TimingAref,  TimingRow,  TimingData and TimingPower registers according to memory AC   parameters.

10.  If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.

11.  Wait for the PhyStatus0.ctrl_locked  bit-fields to change to ‘1’. Check whether PHY DLL is locked.

12.  PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL  should not be off for reliable operation. It can be off  except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force  bit-field to correct value  according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the  PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.

13.  Confirm whether stable clock is  issued minimum 200us after power on.

14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.

15. Wait for minimum 400ns.

16. Issue a PALL command using the DirectCmd register.

17. Issue an  EMRS2 command using the DirectCmd register to program the operating parameters.

18. Issue an  EMRS3 command using the DirectCmd register to program the operating parameters.

19. Issue an  EMRS  command using the DirectCmd register to enable the memory DLLs.

20. Issue a MRS command using the DirectCmd register to reset the memory DLL.

21. Issue a PALL command using the DirectCmd register.

22. Issue two Auto Refresh commands using the  DirectCmd register.

23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.

24. Wait for minimum 200 clock cycles.

25. Issue an  EMRS  command using the DirectCmd register to program the  operating parameters. If OCD calibration is not used, issue an EMRS  command to set OCD Calibration Default. After that, issue an  EMRS  command to exit OCD Calibration Mode  and to program the operating parameters.

26.  If there are two external memory chips, perform steps 14~25 for chip1 memory device.

27. Set the ConControl to turn on an auto refresh counter.

28. If power down modes is required, set the MemControl registers.