SoC Architect

1、Be responsible forthe architecture design of CPUsubsystem in SoC, including the design of cache.

structure、memory hierarchy andbus architecture.  

2、Be responsible forCPU and bus fabric performance evaluation and optimization.  

3、Be responsible forSOC security mechanism design which is based on ARM Trust Zonestructure.  

4、Be responsible forCPU low power design to implement DVFS.  

5、Support the softwareteam to design the framework of the software.

6、Support functionsafety manager to design the function safety mechanism for CPU subsystem.  

7、Co-work with theverification team to formulate the verification plan and continue to cooperateto ensure that the verification coverage reaches the convergence goal.  

8、Co-work with thePhysical implementation team and deeply participate in the back-end task toensure the good PPA result and smoothy timing closure.   

9、Co-Work closely withthe prototype design team to support chip verification and software development.  

10、Co-Work with thePost-silicon validation team to do chip bring-uptest and performance bench marktest.

1、Be familiarand hands on experience to design high performance scaling platform forheterogeneous multiprocessor HPC.  

2、Be familiarand hands on experience to design a cache system for HPC.  

3、Be familiarto co-optimization with the Linux SMP software team  

4、Be familiarwith ARM processor architecture, experienced in ARM high performance Cortex Aseries core integration and implementation.

5、Be familiarwith ARM Trust Zone security schema, Be familiar with MMU and Cachebehavior.   

6、Be familiarwith CHI, ACE, AXI5/4, AHB, APB bus protocols and CMN/CCI/NOC fabricstructure.   

7、Be familiarwith DDR behavior, has rich experience in DDR bandwidth optimization  

8、Beingfamiliar with Fusarequirement andmechanismis a big plus  

9、Beingfamiliar with Linux kernel is a big plus.

10、Beingfamiliar with DFT structure is a plus.   

11、Master’sdegree or above in CS, EEor other related majors. More than 15 years chipdesign experience in CPU or cache system and 5-year SoC architecture experienceat least.