Verilog编程问题

eqgyzgs

我在编写FFT内核的时候在大循环里总是出现下面的错误
Error (10119): Verilog HDL Loop Statement error at Test.v(72): loop with non-constant loop condition must terminate within 250 iterations
Verilog不能支持250层以上的循环么？求高手指教。
有没有现成的FFT内核，希望能参考一下。

一下为代码
/*
FFT code
*/
module Test(CLK_50M,REST,CS,ADCDAT,FULL,BUSY,EXT,OUTDAT);
input CLK_50M,REST,CS,EXT;
input [ADCBit-1:0] ADCDAT;
output FULL,BUSY;
output [63:0] OUTDAT;//计算结果是浮点型
//reg [ADCBit-1:0] ADCDAT;
reg [31:0] OUTDAT;
reg FULL,BUSY;
reg [15:0] CNT;
reg [15:0] N;
reg CLK;
reg [ADCBit-1:0] ADCMEMORY[FFTN-1:0];//输入为实数
reg [31:0] DOREMEMORY[FFTN-1:0],DOIMMEMORY[FFTN-1:0];//输出为复数
reg [15:0] i,j,k;//中间过程变量寄存器
reg [15:0] f,m,l,le,lei,ip;
reg [ADCBit-1:0] temp;
reg [31:0] u[1:0],v[1:0],w[1:0];//x[0]=real,x[1]=image
parameter FFTN=16'd256,//FFT点数
    Pi=3.14159,//pi
    ADCBit=4'd8,//8bit ADC
    CLKDiv=16'd50;//1MHz
   
always @(posedge CLK_50M or negedge REST)
if(!REST) CNT <= 16'h0000;
else if((!CS)&&(CNT!=CLKDiv)) CNT <= CNT+1'b1;
   else CNT <= 16'h0000;
always @(posedge CLK_50M or negedge REST)
if(!REST) CLK <= 1'b0;
else if(CNT==CLKDiv) CLK <= ~CLK;

always @(posedge CLK or negedge REST)//ACD数据输入
if(!REST) N <= 16'h0000;
else if(!CS) begin ADCMEMORY[N] <= ADCDAT;N <= N+1'b1; end

always @(N)
if(N==FFTN-1) FULL <= 1'b1;
else FULL <= 1'b0;

always @(posedge CLK_50M or negedge REST)
if(!REST) begin BUSY <= 1'b0;j <= 16'h0000;f <= FFTN/16'd2; end
else if(N==FFTN-1)
  begin
   BUSY <= 1'b1;
   for(i=16'h0000;i     begin
     if(i       begin
       temp <= ADCMEMORY[j];
       ADCMEMORY[j] <= ADCMEMORY[i];
       ADCMEMORY[i] <= temp;
      end
     k <= FFTN/16'd2;
     while(k<=j)
      begin
       j <= j-k;
       k <= k/16'd2;
      end
     j <= j+k;
    end
   for(i=16'h0000;i     begin
     DOREMEMORY[i] <= ADCMEMORY[i];
     DOIMMEMORY[i] <= 0;
    end
   for(l=16'd1;f!=16'd1;l=l+1'b1) f <= f/2;
   for(m=16'd1;m<=l;m=m+1'b1)
    begin
     le <= 16'd2<<(m-1);
     lei <= le/2;
     u[0] <= 16'd1;
     u[1] <= 16'd0;
     w[0] <= cos(Pi/lei);
     w[1] <= -sin(Pi/lei);
     for(j=0;j<=lei-1;j=j+1'b1)
      begin
       ip <= i+lei;
       EE(DOREMEMORY[ip],DOIMMEMORY[ip],u[0],u[1],v[0],v[1]);
       DOREMEMORY[ip] <= DOREMEMORY[i]-v[0];
       DOIMMEMORY[ip] <= DOIMMEMORY[ip]-v[1];
       DOREMEMORY[i] <= DOREMEMORY[i]+v[0];
       DOIMMEMORY[i] <= DOIMMEMORY[i]+v[1];
      end
     EE(u[0],u[1],w[0],w[1],u[0],u[1]);
    end
   BUSY <= 1'b0;
  end
  
always @(posedge CLK or posedge EXT or negedge BUSY or negedge CS)
if((!CS)&&(!BUSY)&&EXT)
  begin
   OUTDAT <= {DOIMMEMORY[N],DOREMEMORY[N]};
   N <= N-1'b1;
  end
//task EE(ARE,AIM,BRE,BIM,CRE,CIM);
task EE;
input [31:0] ARE,AIM,BRE,BIM;
output [31:0] CRE,CIM;
begin
CRE=ARE*BRE-AIM*BIM;
CIM=ARE*BIM+AIM*BRE;
end
endtask
endmodule

whb_fei

在FPGA中编程，最好多分模块，这样不容易出错，检查时也方便。。。