verification engineer

发布时间:2017年12月12日 11:12    发布者:KT咨询
关键词: ic验证

NO.352-【猎头职位:上海需要两位  verificationengineer 】联系人:Lincy-Cao,邮箱,微信也可查询职位了!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加,欢迎大家关注!

Job description:

1.        Work with designer to get a fulldeep insight on the design and develop stressful test plan for SoC and IPs;

2.        Build test bench and createtestcase to ensure maximum coverage;  

3.        Run simulation in both RTL andnetlist level, debug and fix issues, create test reports;

4.        Develop verification IP whichcan be reused at different level verification;

5.        Co-work with FPGA engineer toprepare test vector, support test and debug;

6.        SoC system performanceprofiling, system stress test;

7.        Explore advanced verificationmethodology, optimize the verification process/environment to improveefficiency and quality;

8.        Support DV manager to do theverification quality control and sign-off the DV task.


1.        MSEE/MSCS degree or equivalent;

2.        Minimum 8 years’ experience indesign verification field;

3.        Good knowledge inSystemVerilog, C/C++ and UVM;

4.        Good knowledge in the SoCarchitecture, AXI/AHB protocol. Experienced in full chip verification plan,execution and sign-off;

5.        Experienced in system performancetest;

6.        Strong communications skillsand capability;

7.        Self-motivated and good teamplayer.

Niceto have

1.        Strong Programming in Perl,Python;

2.        Good digital signal processingbackground and be familiar with video processing algorithm, be familiar withMATLAB;

3.        Experienced in low powerverification;

4.        Be familiar with FPGA debug.

福利:五险一金 年假+奖金

欢迎分享本文,转载请保留出处:     【打印本页】
您需要登录后才可以发表评论 登录 | 立即注册


关于我们  -  服务条款  -  使用指南  -  站点地图  -  友情链接  -  联系我们
电子工程网 © 版权所有   京ICP备16069177号 | 京公网安备11010502021702