上海需要一位 Logic Verification Engineer
发布时间：2015-8-19 16:54
发布者：KT咨询
关键词：
Verification , UVM
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【猎头职位：上海需要一位 Logic Verification Engineer】联系人：David-Chen，邮箱：hr@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！ Responsibilities: Logic Verification Engineer is working on cutting-edge Digital and Mixed-signal IP development for worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic verification or mixed signal verification. Requirements: 1. ME/EE/CS or background in related areas. 2. Research and/or development experience in one or more of the following areas: - Logic verification on the basis of the target system specification； - Mixed-signal model verification on advanced technologies； - Proficiency in programming and/or scripting languages is a plus； - Knowledge on Protocols, High Speed Serdes or DDR is a plus. 3. Experience in one or more of the following application domains, is a plus： - High performance computing system, processor, chipset and ASICs； - High end communication, networking, mobile and data center applications； - Digital signal processing, sensor and Internet of Things； - Other emerging IT technology and industry areas. 4. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus； 5. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.  |
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