上海需要一位 CAD
发布时间：2015-3-25 14:21
发布者：KT咨询
关键词：
verification , CAD
|
【猎头职位：上海需要一位 CAD】联系人：Raymond-Chen 邮箱：hr@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！ Responsibilities: 1. Developverification environment, including test bench and regression system creation,embed it in company customized design flow 2. Build testplan and verify the function of design, support gate level functionalverification, run coverage and regression. Analyze coverage gaps and devise strategyto fill coverage holes 3. Work closelywith different groups to review specification, improve verification plan andmethodology, and ensure full test coverage 4. InterfacingEDA vendors for tools' evaluation, assess vendors' design verificationcapabilities and convergence 5. CAD relateddocumentation. Requirements: 1. BSEE with 5+(or MSEE with 3+) years experience in ASIC verification, complex SOCverification experience is preferred. 2. Solidknowledge in verification methodology. Experience in verification using randomstimulus along with functional coverage and assertion-based verification method.Experience in UVM/OVM, object oriented design principles, Mentor Questasim SV,lower power verification flow with CPF/UPF. 3. Experiencein developing block and chip level test benches, test plan creation. 4. Good attiming analysis, practical skill with gate-level simulation and debuggingtechniques. 5. Familiarwith frontend EDA tools used in all phases of the frontend design cycle (suchas NC, RC, Conformal, ETS form Cadence; Or VCS, DC, Formality, PT fromSynopsys) is a plus. 6. Strongscript programming skills, such as Shell scripting, Perl and Tcl programming,to develop command scripts. 7.Self-motivated to drive for excellence. Must be a team player, and bedisciplined and well organized. 8. Excellentcommunication skills, and be able to work under schedule pressure. 
|
网友评论