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ARM+FPGA架构开发板PCIE2SCREEN示例分析与测试-米尔MYD-JX8MMA7
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使用鼠标点击 ready按钮，demo 窗口会显示连续的视频，说明摄像头、DDR、PCIE接口各部分正常。如果没有接摄像头，该程序会显示杂乱无章的图像。
其中的pRGB保存从FPGA读取的数据。从这句我们可以看出该程序所要求的图像的格式。
{
//int buffer[1920 * 1080];
//int buffer[1024 * 768];
int buffer[1280 * 720];
int i;
if(dev_fd != NULL)
{
fpga_send(dev_fd, 0, buffer, len / 4, 0, 1, 25000);
fpga_recv(dev_fd, 0, buffer, len / 4, 25000);
memcpy(pData, (char *)buffer, len);
return len;
}
else
{
return 0;
}
}
从函数中可以看出，在每次读数据前，该函数先向FPGA写一次数据（数据无意义，和FPGA的状态机有关），每次读入一整帧的数据。
02.FPGA端程序的修改
always @(posedge CLK or posedge RST) begin
if (RST) begin
rLen <= #1 0;
rCount <= #1 0;
rState <= #1 0;
rData <= #1 0;
vout_vs_r <= #1 0;
end
else begin
case (rState)
3'd0: begin // Wait for start of RX, save length
if (CHNL_RX) begin
rLen <= #1 CHNL_RX_LEN;
rCount <= #1 0;
rState <= #1 3'd1;
end
end
3'd1: begin // Wait for last data in RX, save value
if (CHNL_RX_DATA_VALID) begin
rData <= #1 CHNL_RX_DATA;
rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
end
if (rCount >= rLen)begin
rState <= #1 3'd2;
end
end
3'd2: begin // Prepare for TX
if (read_valid) begin
rCount <= #1 0;
rState <= #1 3'd3;
end
end
3'd3: begin // Start TX with save length and data value
if (CHNL_TX_DATA_REN) begin
//rData <= #1 data_in;
rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
if (rCount >= rLen)
rState <= #1 3'd4;
end
end
3'd4: begin
if (vout_vs_r)
rState <= #1 3'd5;
else begin
vout_vs_r <= #1 1;
rState <= #1 3'd4;
rCount <= #1 0;
end
end
3'd5: begin
if (vs_flag) begin
rState <= #1 3'd0;
vout_vs_r <= #1 0;
end
else
rState <= #1 3'd5;
end
endcase
end
end
我们手头没有摄像头进行测试，所以简单修改该程序，使程序发送蓝色渐变色带信号。核心修改如下：
reg [31:0] rColor = 0;
……
assign CHNL_TX_DATA = (read_en)? {rColor, rColor}:64'd0;
……
3'd3: begin // Start TX with save length and data value
if (CHNL_TX_DATA_REN) begin
//rData <= #1 data_in;
// if (rCount % 5 == 4)
rColor <= #1 rColor + 1;
if(rColor >= 255)
rColor <= #1 0;
rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
if (rCount >= rLen)
rState <= #1 3'd4;
end
end
……
