Staff Analog Design Engineer-PLL

发布时间：2023-7-7 10:54 发布者：KT咨询

NO.400-【猎头职位：上海、昆山需要多位 Staff Analog DesignEngineer-PLL】联系人：Sophie-Song,邮箱：hr@kthr.com，微信也可查询职位了！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

岗位职责：

1、Design, evaluate andverify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);

2、Oversee layout andverification activities which include floor plan, LVS and DRC.

岗位要求：

1、Minimum MSEE with 7+ years of relevant industry experience.

2、Good fundamental in analysis and design of analog / mixed-signalcircuits; Experience in Verilog, AHDL and/or Matlab; Ability to do layout andprovide verification/debugging guidance; Solid knowledge of EDA design tools(Analog artist, spectre, HSPICE and nc-verilog ...); Familiar with Computerlanguages such as C, C++, perl;

3、Experience in any of the following areas is preferred: PLL,high-speed I/O’s;

4、Good communication skills and Good oral/written English.

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Staff Analog Design Engineer-PLL

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