上海和北京有新职位啦~
发布时间：2014-2-11 11:15
发布者：KT咨询
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1【猎头职位：上海需要一位“Principle SI/PI Engineer (信号完整性工程师)”】关键词：SI,PI，联系人：Jilly Ji，邮箱: jilly-ji@kthr.com，QQ:443142994，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！ Responsibilities 1.Be responsible for building SI/PI/SiP design flow for High-speed IP Design 2.Proficiency in Cadence tools: Allegro and Sigrity 3.Proficiency in Hspice or spectre simulation, especially in high-speed simulation. 4.Good knowledge in modeling, for example IBIS. 5.Good knowledge in high-speed PCB design. 6.At least eight years experience focus on SiP and SI/PI analysis, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment is required. Qualification 1. Must have BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics. 2. Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English. 3.A minimum of seven years relevant experience in industry. 4.At least five years experience driving SiP/PI/SI project. 5.Will have demonstrated successful completion of 10+ projects as an individual contributor 2【猎头职位：北京需要一位“Principle Verification Engineer”】关键词：Verification ,OVM/UVM 联系人：Jilly Ji，邮箱: jilly-ji@kthr.com，QQ:443142994，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！ Responsibilities 1.Deep understanding on ASIC/SOC design flow 2.Excellent knowledge of advanced verification methodology like eRM/OVM/UVM 3.Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM) 4.Proficiency in System Verilog, System C and/or e (Specman) 5.Developing and using Verification Components (eVC,OVC,UVC,VIP) 6.Developing and using assertion based verification and formal analysis methods 7.Skilled in scripting language,such as Perl,C shell,Python,Makefile 8.Assessing the project verification requirements 9.Operating in a lead role regarding architecting and implementation of project verification environment/solution. 10.May coordinate/lead others within the scope of a defined project Qualification 1.BS degree with 5+ years of applicable experience,MS degree with 4+ years of applicable experience in electrical engineering,microelectronics,comparable engineering science or solid state physics. 2.Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English. 3.A minimum of four years relevant experience in industry. 4.Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project. 5.Will have demonstrated successful completion of 6+ verification projects as an individual contributor 6.Will have DDR project verification experience 
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