Freescale MC56F8257数字信号控制器开发方案

发布时间：2012-6-21 12:31 发布者：1770309616

Freescale公司的MC56F825x/MC56F824x是基于56800E核的数字信号控制器(DSC),集成了DSP的处理功能和MCU功能以及灵活的丰富外设,便于创建高性价比的解决方案.60MHz时的性能为60MIPS,工作电压3.0V-3.6V,工作温度–40℃到+105 ℃,主要用于工业控制,家用电器,智能传感器,消防和安全系统,太阳能逆变器,电池充电和管理,开关电源和管理,马达控制,电表,手持电动工具,医疗设备,仪表和照明镇流器等.本文介绍了MC56F825x/MC56F824x主要特性,框图和56800E核框图, MC56F8257 Tower MCU模块TWR-56F8257主要特性,方框图,电路图和材料清单.

The MC56F825x/MC56F824x is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, it is well-suited for many applications. The MC56F825x/MC56F824x includes many peripherals that are especially useful for cost-sensitive applications, including:

• Industrial control

• Home appliances

• Smart sensors

• Fire and security systems

• Solar inverters

• Battery chargers and management

• Switched-mode power supplies and power management

• Power metering

• Motor control (ACIM, BLDC, PMSM, SR, and stepper)

• Handheld power tools

• Arc detection

• Medical devices/equipment

• Instrumentation

• Lighting ballast

The 56800E core is based on a modified Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.

The MC56F825x/MC56F824x supports program execution from internal memories. Two data operands per instruction cycle can be accessed from the on-chip data RAM. A full set of programmable peripherals supports various applications.

Each peripheral can be independently shut down to save power. Any pin, except Power pins and the Reset pin, can also be configured as General Purpose Input/Outputs (GPIOs).

On-chip features include:

• 60 MHz operation frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• On-chip memory

– 56F8245/46: 48 KB (24K x 16) flash memory; 6 KB (3K x 16) unified data/program RAM

56F8247: 48 KB (24K x 16) flash memory; 8 KB (4K x 16) unified data/program RAM

– 56F8255/56/57: 64 KB (32K x 16) flash memory; 8 KB (4K x 16) unified data/program RAM

• eFlexPWM with up to 9 channels, including 6 channels with high (520 ps) resolution NanoEdge placement

• Two 8-channel, 12-bit analog-to-digital converters (ADCs) with dynamic x2 and x4 programmable amplifier, conversion time as short as 600 ns, and input current-injection protection

• Three analog comparators with integrated 5-bit DAC references

• Cyclic Redundancy Check (CRC) Generator

• Two high-speed queued serial communication interface (QSCI) modules with LIN slave functionality

• Queued serial peripheral interface (QSPI) module

• Two SMBus-compatible inter-integrated circuit (I2C) ports

• Freescale’s scalable controller area network (MSCAN) 2.0 A/B module

• Two 16-bit quad timers (2 x 4 16-bit timers)

• Computer operating properly (COP) watchdog module

• On-chip relaxation oscillator: 8 MHz (400 kHz at standby mode)

• Crystal/resonator oscillator

• Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module

• Inter-module crossbar connection

• Up to 54 GPIOs

• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages

• Single supply: 3.0 V to 3.6 V

MC56F825x/MC56F824x主要特性:

Core

• Efficient 56800E digital signal processor (DSP) engine with modified Harvard architecture

— Three internal address buses

— Four internal data buses

• As many as 60 million instructions per second (MIPS) at 60 MHz core frequency

• 155 basic instructions in conjunction with up to 20 address modes

• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operation

• Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Instruction set supports DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

•JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging

Operation Range

• 3.0 V to 3.6 V operation (power supplies and I/O)

• From power-on-reset: approximately 2.7 V to 3.6 V

• Ambient temperature operating range: –40 ℃ to +105 ℃

Memory

• Dual Harvard architecture that permits as many as three simultaneous accesses to program and data memory

• 48 KB (24K x 16) to 64 KB (32K x 16) on-chip flash memory with 2048 bytes (1024 x 16) page size

• 6 KB (3K x 16) to 8 KB (4K x 16) on-chip RAM with byte addressable

• EEPROM emulation capability using flash

• Support for 60 MHz program execution from both internal flash and RAM memories

• Flash security and protection that prevent unauthorized users from gaining access to the internal flash

Interrupt Controller

• Five interrupt priority levels

— Three user programmable priority levels for each interrupt source: Level 0, 1, 2

— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, and SWI3 instruction Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, and EOnCE trace buffer

— Lowest-priority software interrupt: level LP

• Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt subroutine

• Two programmable fast interrupts that can be assigned to any interrupt source

• Notification to system integration module (SIM) to restart clock out of wait and stop states

• Ability to relocate interrupt vector table

The masking of interrupt priority level is managed by the 56800E core.

Peripheral Highlights

• One Enhanced Flex Pulse Width Modulator (eFlexPWM) module

— Up to nine output channels

— 16-bit resolution for center aligned, edge aligned, and asymmetrical PWMs

— Each complementary pair can operate with its own PWM frequency based and deadtime values

– 4 Time base

– Independent top and bottom deadtime insertion

— PWM outputs can operate as complimentary pairs or independent channels

— Independent control of both edges of each PWM output

— 6-channel NanoEdge high resolution PWM

– Fractional delay for enhanced resolution of the PWM period and edge placement

– Arbitrary eFlexPWM edge placement - PWM phase shifting

– NanoEdge implementation: 520 ps PWM frequency resolution

— 3 Channel PWM with full Input Capture features

– Three PWM Channels - PWMA, PWMB, and PWMX

– Enhanced input capture functionality

— Support for synchronization to external hardware or other PWM

— Double buffered PWM registers

– Integral reload rates from 1 to 16

– Half cycle reload capability

— Multiple output trigger events can be generated per PWM cycle via hardware

— Support for double switching PWM outputs

— Up to four fault inputs can be assigned to control multiple PWM outputs

– Programmable filters for fault inputs

— Independently programmable PWM output polarity

— Individual software control for each PWM output

— All outputs can be programmed to change simultaneously via a FORCE_OUT event

— PWMX pin can optionally output a third PWM signal from each submodule

— Channels not used for PWM generation can be used for buffered output compare functions

— Channels not used for PWM generation can be used for input capture functions

— Enhanced dual edge capture functionality

— Option to supply the source for each complementary PWM signal pair from any of the following:

– Crossbar module outputs

– External ADC input, taking into account values set in ADC high and low limit registers

• Two independent 12-bit analog-to-digital converters (ADCs)

— 2 x 8 channel external inputs Built-in x1, x2, x4 programmable gain pre-amplifier

— Maximum ADC clock frequency: up to 10 MHz

– Single conversion time of 8.5 ADC clock cycles (8.5 x 100 ns = 850 ns)

– Additional conversion time of 6-ADC clock cycles (6 x 100 ns = 600 ns)

— Sequential, parallel, and independent scan mode

— First 8 samples have Offset, Limit and Zero-crossing calculation supported

— ADC conversions can be synchronized by eFlexPWM and timer modules via internal crossbar module

— Support for simultaneous and software triggering conversions

— Support for multi-triggering mode with a programmable number of conversions on each trigger

• Inter-module Crossbar Switch (XBAR)

— Programmable internal module connections among the eFlexPWM, ADCs, Quad Timers, 12-bit DAC, HSCMPs, and package pins

— User-defined input/output pins for PWM fault inputs, Timer input/output, ADC triggers, and Comparator outputs

• Three analog comparators (CMPs)

— Selectable input source includes external pins, internal DACs

Programmable output polarity

— Output can drive timer input, eFlexPWM fault input, eFlexPWM source, external pin output, and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

— 32-tap programmable voltage reference per comparator

• One 12-bit digital-to-analog converter (12-bit DAC)

— 12-bit resolution

— Power down mode

— Output can be routed to internal comparator, or off chip

• Two four-channel 16-bit multi-purpose timer (TMR) modules

— Four independent 16-bit counter/timers with cascading capability per module

— Up to 120 MHz operating clock

— Each timer has capture and compare and quadrature decoder capability

— Up to 12 operating modes

— Four external inputs and two external outputs

• Two queued serial communication interface (QSCI) modules with LIN slave functionality

— Up to 120 MHz operating clock

— Four-byte-deep FIFOs available on both transmit and receive buffers

— Full-duplex or single-wire operation

— Programmable 8- or 9-bit data format

— 13-bit integer and 3-bit fractional baud rate selection

— Two receiver wakeup methods:

– Idle line

– Address mark

— 1/16 bit-time noise detection

— Support LIN slave operation

• One queued serial peripheral interface (QSPI) module

— Full-duplex operation

— Four-word deep FIFOs available on both transmit and receive buffers

— Master and slave modes

— Programmable length transactions (2 to 16 bits)

Programmable transmit and receive shift order (MSB as first or last bit transmitted)

— Maximum slave module frequency = module clock frequency/2

— 13-bit baud rate divider for low speed communication

• Two inter-integrated circuit (I2C) ports

— Operation at up to 100 kbps

— Support for master and slave operation

— Support for 10-bit address mode and broadcasting mode

— Support for SMBus, Version 2

• One Freescale Scalable Controller Area Network (MSCAN) module

— Fully compliant with CAN protocol Version 2.0 A/B

— Support for standard and extended data frames

— Support for data rate up to 1 Mbit/s

— Five receive buffers and three transmit buffers

• Computer operating properly (COP) watchdog timer capable of selecting different clock sources

— Programmable prescaler and timeout period

— Programmable wait, stop, and partial powerdown mode operation

— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected

— Choice of clock sources from four sources in support of EN60730 and IEC61508:

– On-chip relaxation oscillator

– External crystal oscillator/external clock source

– System clock (IP bus to 60 MHz)

• Power supervisor (PS)

— On-chip linear regulator for digital and analog circuitry to lower cost and reduce noise

— Integrated low voltage detection to generate warning interrupt if VDD is below low voltage detection (LVI) threshold

— Integrated power-on reset (POR)

– Reliable reset process during power-on procedure

– POR is released after VDD passes low voltage detection (LVI) threshold

— Integrated brown-out reset

Run, wait, and stop modes

• Phase lock loop (PLL) providing a high-speed clock to the core and peripherals

— 2x system clock provided to Quad Timers and SCIs

— Loss of lock interrupt

— Loss of reference clock interrupt

• Clock sources

— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for normal operation

— External clock: crystal oscillator, ceramic resonator, and external clock source

• Cyclic Redundancy Check (CRC) Generator

— Hardware CRC generator circuit using 16-bit shift register

— CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial

— Error detection for all single, double, odd, and most multi-bit errors

— Programmable initial seed value

— High-speed hardware CRC calculation

— Optional feature to transpose input data and CRC result via transpose register, required on applications where bytes are in LSb (Least Significant bit) format.

• Up to 54 general-purpose I/O (GPIO) pins

— 5 V tolerant I/O

— Individual control for each pin to be in peripheral or GPIO mode

Individual input/output direction control for each pin in GPIO mode

— Individual control for each output pin to be in push-pull mode or open-drain mode

— Hysteresis and configurable pullup device on all input pins

— Ability to generate interrupt with programmable rising or falling edge and software interrupt

— Configurable drive strength: 4 mA / 8 mA sink/source current

• JTAG/EOnCE debug programming interface for real-time debugging

IEEE 1149.1 Joint Test Action Group (JTAG) interface

EOnCE interface for real-time debugging

Power Saving Features

• Low-speed run, wait, and stop modes: as low as 781 Hz clock provided by OCCS and internal ROSC

• Large regulator standby mode available for reducing power consumption at low-speed mode

• Less than 30 μs typical wakeup time from stop modes

• Each peripheral can be individually disabled to save power

图1.MC56F825x方框图

图2.56800E核框图

图3.MC56F824x相移电源转换器框图

图4.MC56F825x高性能PMSM伺服系统框图

TWR-56F8257: MC56F8257 Tower MCU模块

The MC56F8257 Tower MCU module (TWR-56F8257) is a cost-effective evaluation, demonstration and development board. The TWR-56F8257 can operate stand-alone or as the main control board in a Tower System with peripheral modules. It can also be used as the main control board with an APMOTOR56F8000E motor control board.

TWR-56F8257主要特性:

The following list summarizes the features of the TWR-56F8257:

• Tower-compatible microcontroller module

• Selectable power sources:

USB

Barrel connector

Motor control board

Tower elevator board

• Filtered power for VDDA and VSSA on the MC56F8257DSC

• MC56F8257 digital signal controller (DSC) in an 64 LQFP package

• Optional 8 MHz crystal circuit for the MC56F8257 DSC

• Nine LEDs controlled by the MC56F8257 DSC

• Motor control board connector for the APMOTOR56F8000E motor control board

• Auxiliary signal connector

• Four thermistors for single-ended or differential analog inputs to the MC56F8257 DSC

• CAN transceiver, header and termination

• Two push buttons for user input or interrupts to the MC56F8257 DSC

• Reset push button for the MC56F8257 DSC

• JTAG header for the MC56F8257 DSC with header to disconnect from OSBDM

• Headers to connect SCI signals to either USB bridge or elevator board

• Expansion via primary elevator connector

• MC9S08JM60 MCU with a 4 MHz crystal provides:

Open source debug (OSBDM) circuit

USB to SCI bridge

Header to select between OSBDM and USB to SCI bridge functions

Bootloader enable header

BDM header for the MC9S08JM60 MCU

Status and target power indicator LEDs

Control of semiconductor switch to enable power to board from USB

Voltage translators between 5V MC9S08JM60 MCU chip and 3.3V MC56F8257 DSC chip