cpld与8051的总线接口vhdl设计源码

2009年11月13日 12:11    诸葛孔明
关键词: CPLD , VHDL , 接口 , 源码 , 总线
8051工作频率为11.0592MHZ  CPLD(EPM7128SLC15)的工作频率为16.0000MHZ(有源晶振)



  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_unsigned.all;
  4. entity cpldbus51 is
  5. port (            
  6.   Clk: in STD_LOGIC;                     --Clock    16MHZ  
  7.   Clr: in STD_LOGIC;         --Clear   high
  8.   P0: inout STD_LOGIC_VECTOR (7 downto 0);   --8052 Port 0
  9.   P2: in STD_LOGIC_VECTOR (7 downto 0);    --8052 Port 2
  10.   ALE: in STD_LOGIC;                         --8052 ALE
  11. --  PSEN: in STD_LOGIC;         --8052'Psen
  12. --  INT0:out  STD_LOGIC;                       --8052 INT0
  13.   Wr: in STD_LOGIC;         --8052'Wr
  14.   Rd: in STD_LOGIC;         --8052'Rd
  15. ---------------------------
  16.   Pina:out STD_LOGIC;                     ---output
  17. -----------------------
  18.   nCS8255: out STD_LOGIC;           --select 8255
  19.   RamBank: out STD_LOGIC_VECTOR (1 downto 0);--Ram68128a bank switch   A15 A16
  20.   nCsFlashRam: out STD_LOGIC;       --select Flash Rom   CE
  21.   FlashRomBank: out STD_LOGIC_VECTOR (2 downto 0) --Flash Rom switch  A14 A15 A16

  22. );
  23. end cpldbus51;

  24. architecture cpldbus51 of cpldbus51 is           
  25. ------------------------------------------------------------------------------
  26. signal Addr: std_logic_vector(15 downto 0);  --16bit address
  27. signal ALE_Sample:STD_LOGIC;
  28. signal RamBankReg: STD_LOGIC_VECTOR (1 downto 0);--Ram bank switch reg, 4 banks, 4*32K=128k bytes
  29. signal FlashRomBankReg: STD_LOGIC_VECTOR (2 downto 0);--Flash Rom bank switch reg, 8 banks, 8*16K=128k bytes
  30. --Rd Sample
  31. signal RdSample:std_logic; --for Rd Sample
  32. --WR Sample
  33. signal WrSample0:std_logic; --Wr for Sample
  34. signal WrSample1:std_logic;
  35. signal WrSample2:std_logic;
  36. signal WrSample3:std_logic;
  37. signal WrSample4:std_logic;
  38. signal WrSample5:std_logic;
  39. --Wr Sample output
  40. signal Wr_en:std_logic;
  41. --Clr Sample
  42. signal ClrSample0:std_logic; -- for Clr Sample
  43. signal ClrSample1:std_logic;
  44. signal ClrSample2:std_logic;
  45. signal ClrSample3:std_logic;
  46. signal ClrSample4:std_logic;
  47. signal ClrSample5:std_logic;
  48. signal ClrSample6:std_logic;
  49. signal ClrSample7:std_logic;
  50. signal ClrSample8:std_logic;
  51. signal ClrSample9:std_logic;
  52. --Clr Sample output
  53. signal Clr_en:std_logic;
  54. ------------------------------------------------------------------------------
  55. --output Reg
  56. signal PinaReg:std_logic;
  57. begin  
  58. --------------------------------------------
  59. --Sample Clr signal  
  60. ClrSample_p:process(Clk)
  61. begin
  62. if Clk'event and Clk='1' then
  63.   ClrSample0<=Clr;
  64.   ClrSample1<=ClrSample0;
  65.   ClrSample2<=ClrSample1;
  66.   ClrSample3<=ClrSample2;
  67.   ClrSample4<=ClrSample3;
  68.   ClrSample5<=ClrSample4;
  69.   ClrSample6<=ClrSample5;
  70.   ClrSample7<=ClrSample6;
  71.   ClrSample8<=ClrSample7;
  72.   ClrSample9<=ClrSample8;
  73. end if;
  74. end process;      
  75. ---------------------------------------
  76. --Clr Enable Signal
  77. Clr_en_p:process(Clk)
  78. begin   
  79. if Clk'event and Clk='1' then
  80.   if      ClrSample0='1' and ClrSample1='1'
  81.    and ClrSample2='1' and ClrSample3='1'
  82.    and ClrSample4='1' and ClrSample5='1'
  83.    and ClrSample6='1' and ClrSample7='1'
  84.    and ClrSample8='1' and ClrSample9='1' then
  85.    Clr_en<='1';
  86.   else
  87.    Clr_en<='0';
  88.   end if;
  89. end if;
  90. end process;      
  91. ------------------------------------------------
  92. --sample ALE signal
  93. ALE_p:process(Clk)
  94. begin
  95.   if Clk'event and Clk='1' then
  96.    if Clr_en='1' then
  97.     ALE_Sample<='0';
  98.    else
  99.     ALE_Sample<=ALE;
  100.    end if;
  101.   end if;
  102. end process;
  103. -------------------------------------------------      
  104. --Address Latch
  105. Address_p:process(Clk)
  106. begin
  107.   if Clk'event and Clk='1' then
  108.    if Clr_en='1' then
  109.      Addr<="0000000000000000";
  110.    elsif ALE_Sample='1' then
  111.     Addr<=P2&P0;
  112.    end if;
  113.   end if;
  114. end process;            
  115. -------------------------------------
  116. --Sample Wr
  117. WrSample_p:process(Clk)
  118. begin
  119. if Clk'event and Clk='1' then
  120.   if Clr_en='1' then
  121.    WrSample0<='1';
  122.    WrSample1<='1';
  123.    WrSample2<='1';
  124.    WrSample3<='1';
  125.    WrSample4<='1';
  126.    WrSample5<='1';
  127.   else
  128.    WrSample0<=Wr;
  129.    WrSample1<=WrSample0;
  130.    WrSample2<=WrSample1;
  131.    WrSample3<=WrSample2;
  132.    WrSample4<=WrSample3;
  133.    WrSample5<=WrSample4;
  134.   end if;
  135. end if;
  136. end process;
  137. ---------------------------------------
  138. --internal Wr enable signal
  139. WrEn_p:process(WrSample0,WrSample1,WrSample2,WrSample3,WrSample4,WrSample5)
  140. begin
  141. if (WrSample0='0' and  WrSample1='0'
  142.   and WrSample2='0' and WrSample3='0'
  143.   and WrSample4='1'and WrSample5='1')then
  144.   Wr_en<='1';
  145. else
  146.   Wr_en<='0';
  147. end if;
  148. end process;      
  149. ----------------------------------------
  150. --Rd Sample
  151. RdSample_p:process(Clk)
  152. begin
  153. if Clk'event and Clk='1' then
  154.   if Clr_en='1' then
  155.    RdSample<='1';
  156.   else
  157.    RdSample<=Rd;
  158.   end if;
  159. end if;
  160. end process;

  161. -----------------------------------
  162. --Flash Rom Chip select signal
  163. CS_Flash_p:process(Addr)
  164. begin
  165. if Addr(15 downto 14)="10" then            --Address:8000h--BFFFh
  166.      nCsFlashRam<='0';
  167. else
  168.   nCsFlashRam<='1';
  169. end if;
  170. end process;
  171. -----------------------------------
  172. -- 8255 Chip select signal
  173. cs8255_p:process(Addr)
  174. begin
  175.   if Addr(15 downto 2)="11000000000000" then  --C000h--C003h
  176.    nCS8255<='0';
  177.   else
  178.    nCS8255<='1';
  179.   end if;
  180. end process;      
  181. -----------------------------------
  182. -----------------------------------
  183. -- Ram Bank Switch Reg
  184. Ram_bank_p:process(Clk)
  185. begin      
  186. if Clk'event and Clk='1' then
  187.   if Clr_en='1' then
  188.       RamBankReg<="00";  
  189.   elsif Addr="1100000000000100" and Wr_en='1' then    --Address:C004h
  190.          RamBankReg<=P0(1 downto 0);
  191.   end if;
  192. end if;
  193. end process;
  194. RamBank<=RamBankReg;      
  195. ----------------------------------
  196. ----------------------------------
  197. --Flash Rom Switch Reg
  198. Flash_bank_p:process(Clk)
  199. begin      
  200. if Clk'event and Clk='1' then
  201.   if Clr_en='1' then
  202.    FlashRomBankReg<="000";
  203.   elsif Addr="1100000000000101"  and Wr_en='1' then      --Address:C005h
  204.    FlashRomBankReg<=P0(2 downto 0);
  205.   end if;
  206. end if;
  207. end process;
  208. FlashRomBank<=FlashRomBankReg;   
  209. --------------------------------
  210. --------------------------------
  211. --Rd process
  212. -- now just two in-builde register
  213. Rd_p:process(RdSample,Addr,RamBankReg,FlashRomBankReg)
  214. begin
  215. if    Addr="1100000000000100"  and RdSample='0' then    --C004h
  216.      P0<="000000"&RamBankReg;
  217. elsif Addr="1100000000000101"  and RdSample='0' then    --C005h
  218.   P0<="00000"&FlashRomBankReg;
  219. else
  220.   P0<="ZZZZZZZZ";
  221. end if;
  222. end process;   
  223. -------------------------------   
  224. Pina_p:process(Clk)
  225. begin
  226. if Clk'event and Clk='1' then
  227.   if Clr_en='1' then
  228.    PinaReg<='0';
  229.   elsif Addr="1100000000000110"  and Wr_en='1' then      --C006h
  230.    PinaReg<=P0(0);
  231.   end if;
  232. end if;
  233. end process;   
  234. Pina<=PinaReg;   
  235. end cpldbus51;

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wsjc1999 发表于 2009-11-19 20:17:11
应该有用,谢谢。
lising 发表于 2010-9-26 16:09:50
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